Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
-------------------------------------------------------------------

Required properties:
- compatible            : Should be "xlnx,zynqmp-qspi-1.0".
- reg                   : Physical base address and size of GQSPI registers map.
- interrupts            : Property with a value describing the interrupt
                          number.
- interrupt-parent      : Must be core interrupt controller.
- clock-names           : List of input clock names - "ref_clk", "pclk"
                          (See clock bindings for details).
- clocks                : Clock phandles (see clock bindings for details).

Optional properties:
- num-cs                : Number of chip selects used.
- has-io-mode           : boolean property describes the controller operating
                          mode. if exists controller will operate in IO mode
                          else dma mode.
- is-dual               : zynqmp qspi support for dual-parallel mode configuration
                          value should be 1.
- is-stacked            : zynqmp qspi support for stacked mode configuration.
                          to enable this mode, is-dual should be 0 and is-stacked
                          should be 1.

Example:
        qspi: spi@ff0f0000 {
                compatible = "xlnx,zynqmp-qspi-1.0";
                clock-names = "ref_clk", "pclk";
                clocks = <&misc_clk &misc_clk>;
                interrupts = <0 15 4>;
                interrupt-parent = <&gic>;
                num-cs = <1>;
                reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
        };